High-speed source synchronous systems require highly accurate alignment between data bits within a data eye and highly accurate placement of the sampling dock within the center of the composite data eye to maximize performance. The ideal alignment of the data bits and the ideal placement of the sampling clock are typically determined using complex training algorithms designed to induce the worst case data eye caused from non-ideal factors, such as intersymbol interference (ISO, supply noise, channel reflections, and the like. This training process often becomes highly involved and requires a significant amount of time to execute. Furthermore, the training algorithm can only determine the ideal placement for a given voltage and temperature point at the time of calibration. Over time, this ideal positioning will change due to voltage and temperature changes, which will induce both internal and external delay changes within the system. These changing delays will cause the system timing to drift away from its ideal location and will result in performance loss.
The most accurate process for compensating for drift is to recalibrate the system using the complex training process. However, using the complex training process to recalibrate the system has the adverse effect of halting the data flow during recalibration, which reduces throughput of the system. It is desirable to minimize the amount of time required to recalibrate the system in order to minimize the impact the recalibration process has on the overall system. At the same time, the recalibration process should maintain the accuracy of the original timing intensive (complex) training algorithm as voltage and temperature change.